(1) Field of the Invention
This invention relates to a semiconductor integrated circuit device, a circuit design apparatus, and a circuit design method and, more particularly, to a semiconductor integrated circuit device with a multi-layer wiring structure and a circuit design apparatus and circuit design method for designing interlayer interconnection in semiconductor integrated circuits with a multi-layer wiring structure.
(2) Description of the Related Art
Some semiconductor integrated circuit device have a multi-layer electrode wiring. Computer-aided design (CAD) or the like is generally used for designing semiconductor integrated circuit device with a multi-layer electrode wiring. When circuits are designed, wiring width should be determined with the performance and the like of manufacturing facilities taken into consideration so that high-quality products can be manufactured. The minimum wiring width depends on the accuracy and the like of exposure and etching by manufacturing facilities.
Conventionally, great attention has not been given to the maximum wiring width. In recent years, however, the fact that placing a limit on the maximum wiring width also improves the quality of products has become known.
For example, if an aluminum wiring is too wide, a projection (hillock) will appear due to heat treatment after the formation of the wiring. A wider aluminum wiring is apt to cause a higher hillock. An insulating film formed on a wiring layer will become thin at a place where a hillock has appeared. If a hillock is too high, wirings in lower and an upper layers can short-circuit. Therefore, by limiting wiring width to the maximum width, a wiring short circuit caused by a hillock can be prevented.
Furthermore, if an aluminum wiring is too wide, its upper corners (edge portions) will be rounded out during the process of forming it by etching. That is to say, the top of the wiring will round out. This is a factor that interferes with the planarization of the surface of a chip in a semiconductor circuit device. Failure to planarize the surface of a chip in a semiconductor circuit device will cause the following problems.
In general, with a semiconductor device having the structure of multi-layer wiring structure, each layer must be made planar in order to reduce difference in level on the surface of a semiconductor chip. The reason for this is that the irregularities of the surface of a layer will be accumulated each time an upper layer is formed. That is to say, with an increase in the number of layers the irregularities of the surface of a layer become severer.
Severe irregularities have a bad influence on the process for forming wirings, resulting in a low yield at the time of manufacture.
In recent years copper wirings are sometimes used in order to reduce wiring resistance. The process for forming copper wirings is different from that for forming aluminum wirings. First, grooves are formed by etching in an area on an interlayer insulating film where wirings are to be formed. Then the top of the interlayer insulating film is plated with copper so that the formed grooves is filled up with it. Then extra copper is polished away by a technique called chemical mechanical polishing (CMP) except copper which has filled up the grooves for wirings.
If wiring width is too wide in this process for forming copper wirings, CMP will polish away more copper in grooves for wirings than need be. This leads to dishing. That is to say, a large cavity is formed in the middle of the top of a wiring. This cavity will interfere with the planarization of the surface of a chip. This is the same with an aluminum wiring.
For the various reasons described above, semiconductor circuits must be designed so that wiring width will not exceed the maximum width.
In order to limit wiring width to the maximum width, a pole-shaped insulating area called a pillar or slit is located in an area where wirings should be formed. For example, Japanese Patent Laid-Open Publication No.Hei4-116827 narrows wiring width by locating a plurality of slits in an aluminum electrode wiring in a lower layer in an area where the aluminum electrode wiring in the lower layer and an aluminum electrode wiring in an upper layer overlap.
By the way, interlayer connection can be made by locating a plurality of conductive paths called vias in an area where a wiring in a lower layer and a wiring in an upper layer overlap. If wirings in different layers are connected by a plurality of vias and one of the vias is faulty, the electric connection between the wirings can be maintained through the other vias. Furthermore, interlayer connection by a plurality of vias will reduce interlayer wiring resistance. This carries the advantages of, for example, being able to improve a yield. Sometimes a via is referred to as a via hole, contact hole, or through hole.
The wider an area on a wiring (connection terminal) where vias should be formed is, the greater the number of vias which can be formed becomes. As a result, good electric characteristics can be obtained. However, if the area of a connection terminal is too large, the occurrence of a hillock of an aluminum wiring around the connection terminal, the occurrence of the roundness of an aluminum wiring at the edge portion of a connection terminal, or the occurrence of dishing on the top of a copper wiring at a connection terminal cannot be prevented. This will lead to a low yield. Therefore, a semiconductor integrated circuit device with a connection terminal, the area of which is sufficient to arrange vias and at which wiring width is limited to the maximum width, is needed.
In order to address such problems, the present invention was made. In other words, an object of the present invention is to provide a semiconductor integrated circuit device in which wirings in different layers are connected electrically by vias and in which wiring width at a connection terminal is limited to the maximum width.
Another object of the present invention is to provide an apparatus and method for designing circuits that can easily design semiconductor circuits in which wiring width in an area for connecting different layers electrically is limited to the maximum width and in which a sufficient number of vias are arranged.
In order to achieve the former object, a semiconductor integrated circuit device with a multi-layer wiring structure is provided. This semiconductor integrated circuit device comprises a first wiring located in a first layer, a second wiring located in a second layer laid over the first layer, and a plurality of vias formed between the first layer and the second layer and arranged annularly in an area where the first wiring and the second wiring overlap.
Furthermore, in order to achieve the latter object, a circuit design apparatus for designing interlayer interconnection in semiconductor integrated circuits with a multi-layer wiring structure is provided. This circuit design apparatus comprises first virtual wiring generating means for generating a first virtual wiring being narrower than a first wiring in a first layer, first via generating means for generating at least one via in an area between a second wiring in a second layer laid over the first layer and the first virtual wiring generated by the first virtual wiring generating means, second virtual wiring generating means for generating a second virtual wiring being narrower than the second wiring in the second layer, and second via generating means for generating at least one via in an area between the first wiring and the second virtual wiring generated by the second virtual wiring generating means.
Moreover, in order to achieve the latter object, a circuit design apparatus for designing interlayer interconnection in semiconductor integrated circuits with a multi-layer wiring structure is provided. This circuit design apparatus comprises edge judging means for judging the edge of an area where a first wiring in a first layer and a second wiring in a second layer overlap and via generating means for generating a plurality of vias in an annular area of a predetermined width from an edge judged by the edge judging means.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.